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1. features ? write protect pin for hardware data protection ? utilizes different array protection compared to the at24c02b ? low-voltage and standard-voltage operation ?1.8(v cc =1.8vto5.5v) ? internally organized 25 6 x 8 (2k) ? two-wire serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 1 mhz (5v) and 400 khz (1.8v, 2.5v, 2.7v) clock rate ? 8-byte page ? partial page writes allowed ? self-timed write cycle (5 ms max) ? high reliability ? endurance: one million write cycles ? data retention: 100 years ? 8-lead pdip, 8-lead jedec soic and 8-lead tssop packages ? die sales: wafer form, tape and reel, and bumped wafers 2. description the at24hc02b provides 2048 bits of serial electrically erasable and programmable read-only memory (eeprom) organized as 256 words of 8 bits each. the device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. the at24hc02b is available in space-saving 8-lead pdip, 8-lead jedec soic and 8-lead tssop packages and is accessed via a two-wire serial interface. in addition, the entire family is available in 1.8v (1.8v to 5.5v) version. table 2-1. pin configuration pin name function a0?a2 address inputs sda serial data scl serial clock input wp write protect two-wire serial eeprom 2k (256 x 8) at24hc02b not recommended for new design. replaced by at24hc02c. rev. 5134e?seepr?3/08 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead pdip 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead soic 1 2 3 4 8 7 6 5 a0 a1 a2 gnd vcc wp scl sda 8-lead tssop
2 5134e?seepr?3/08 at24hc02b figure 2-1. block diagram absolute maximum ratings* operating temperature ???????????????????????????????????? ? 55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ???????????????????????????????????????? ? 65 ? c to +150 ? c voltage on any pin with respect to ground ???????????????????????????????????????? ? 1.0v to +7.0v maximum operating voltage .......................................... 6.25v dc output current........................................................ 5.0 ma start stop logic vcc gnd wp scl sda a 2 a 1 a 0 serial control logic en h.v. pump/timing eeprom data recovery serial mux x dec d out /ack logic comp load inc data word addr/counter y dec r/w d out d in load device address comparator
3 5134e?seepr?3/08 at24hc02b 3. pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open- drain driven and may be wire-ored with any number of other open-drain or open collector devices. device/page addresses (a2, a1, a0): the a2, a1 and a0 pins are device address inputs that must be hardwired for the at24hc02b. as many as eight 2k devices may be addressed on a single bus system. (device addressing is discussed in detail under device addressing, page 8 ). write protect (wp): the at24hc02b has a wp pin that provides hardware data protec- tion. the wp pin allows normal read/write operations when connected to ground (gnd). when the wp pin is connected to v cc , the write protection feature is enabled and operates as shown. table 3-1. write protect wp pin status part of the array protected 24hc02b at v cc upper half (1k) array at gnd normal read/write operations
4 5134e?seepr?3/08 at24hc02b 4. memory organization at24hc02b, 2k serial eeprom: the 2k is internally organized with 32 pages of 8 bytes each. random word addressing requires an 8-bit data word address. note: 1. this parameter is characterized and is not 100% tested. note: 1. v il min and v ih max are reference only and are not tested. table 4-1. pin capacitance (1) applicable over recommended operating range from t ai =25 ? c,f=1.0mhz,v cc = +1.8v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o =0v c in input capacitance (a 0 ,a 1 ,a 2 , scl) 6 pf v in =0v table 4-2. dc characteristics applicable over recommended operating range from: t ai = ? 40 ? c to +85 ? c, v cc = +1.8v to +5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.8 5.5 v v cc2 supply voltage 2.5 5.5 v v cc3 supply voltage 2.7 5.5 v v cc4 supply voltage 4.5 5.5 v i cc supply current v cc = 5.0v read at 100 khz 0.4 1.0 ma i cc supply current v cc = 5.0v write at 100 khz 2.0 3.0 ma i sb1 standby current v cc =1.8v v in =v cc or v ss 0.6 3.0 a i sb2 standby current v cc =2.5v v in =v cc or v ss 1.4 4.0 a i sb3 standby current v cc =2.7v v in =v cc or v ss 1.6 4.0 a i sb4 standby current v cc =5.0v v in =v cc or v ss 8.0 18.0 a i li input leakage current v in =v cc or v ss 0.10 3.0 a i lo output leakage current v out =v cc or v ss 0.05 3.0 a v il input low level (1) ? 0.6 v cc x 0.3 v v ih input high level (1) v cc x 0.7 v cc + 0.5 v v ol2 output low level v cc =3.0v i ol = 2.1 ma 0.4 v v ol1 output low level v cc =1.8v i ol = 0.15 ma 0.2 v
5 5134e?seepr?3/08 at24hc02b note: 1. this parameter is ensured by characterization only. table 4-3. ac characteristics applicable over recommended operating range from t ai = ? 40 ? cto+85 ? c, v cc = +1.8v to +5.5v, cl = 1 ttl gate and 100 pf (unless otherwise noted) symbol parameter 1.8, 2.5, 2.7 5.0-volt units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.2 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time 50 40 ns t aa clock low to data out valid 0.1 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start 1.2 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start setup time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 100 ns t su.sto stop setup time 0.6 .25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 5.0v, 25 ? c, byte mode 1 million write cycles
6 5134e?seepr?3/08 at24hc02b 5. device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 5-1 ). data changes during scl high periods will indicate a start or stop condition as defined below. figure 5-1. data validity start condition: a high-to-low transition of sda with scl high is a start condition that must precede any other command (see figure 5-2 ). figure 5-2. start and stop definition stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see fig- ure 5-2 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. . the eeprom sends a ?0? to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the at24hc02b features a low-power standby mode that is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. sda scl data stable data stable data change sda scl start stop
7 5134e?seepr?3/08 at24hc02b 2-wire software reset: after an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) clock up to 9 cycles, (b) look for sda high in each cycle while scl is high, (c) create a start condition as sda is high. the device is ready for next communication after above steps have been completed. figure 5-3. software reset figure 5-4. bus timing figure 5-5. write cycle timing notes: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. start bit stop bit start bit dummy clock cycles scl sda 12 3 89 scl sda in sda out t f t high t low t low t r t aa t dh t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta t wr (1) stop condition start condition wordn ack 8th bit scl sda
8 5134e?seepr?3/08 at24hc02b figure 5-6. output acknowledge 6. device addressing the 2k eeprom device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation, as shown in figure 6-1 . figure 6-1. device address the device address word consists of a mandatory ?1?, ?0? sequence for the first four most signif- icant bits as shown. this is common to all the eeprom devices. the next three bits are the a2, a1 and a0 device address bits for the 2k eeprom. these three bits must compare to their corresponding hardwired input pins. the eighth bit of the device address is the read/write operation select bit. a read operation is ini- tiated if this bit is high, and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a ?0?. if a compare is not made, the chip will return to a standby state. scl data in data out start acknowledge 9 8 1 msb 2k lsb 1 a 2 a 0 a 1 r/w 00 1
9 5134e?seepr?3/08 at24hc02b 7. write operations byte write: a write operation requires an 8-bit data word address following the device address word and acknowledgement. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a ?0? and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time, the eeprom enters an inter- nally-timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle, and the eeprom will not respond until the write is complete, see figure 7-1 on page 9 . figure 7-1. byte write page write: the 2k eeprom is capable of an 8-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2k) more data words. the eeprom will respond with a ?0? after each data word received. the microcontroller must terminate the page write sequence with a stop condition, see figure 7-2 . figure 7-2. page write the data word address lower three (2k) bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than eight (2k) data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally-timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0? allowing the read or write sequence to continue. s t a r t m s b s t o p w r i t e sda line device address word address data a c k a c k a c k r / w s t a r t m s b s t o p w r i t e sda line device address word address (n) data (n) data (n + 1) data (n + x) a c k a c k a c k a c k a c k r / w
10 5134e?seepr?3/08 at24hc02b 8. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to ?1?. there are three read operations: current address read, random address read and sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address ?roll over? during read is from the last byte of the last memory page to the first byte of the first page. the address ?roll over? during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to ?1? is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input ?0? but does generate a following stop condition, see figure 8-1 . figure 8-1. current address read random read: a random read requires a ?dummy? byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a ?0? but does generate a following stop condition, see figure 8-2 . figure 8-2. random read s t a r t r e a d m s b s t o p sda line device address data a c k n o a c k r / w s t a r t s t a r t m s b s t o p w r i t e r e a d sda line device address dummy write word address n device address data n a c k a c k a c k n o a c k r / w m s b m s b
11 5134e?seepr?3/08 at24hc02b sequential read: sequential reads are initiated by either a current address read or a ran- dom address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will ?roll over? and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a ?0? but does generate a following stop condition, see figure 8-3 . figure 8-3. sequential read
12 5134e?seepr?3/08 at24hc02b notes: 1. ?-b? denotes bulk. 2. ?-t? denotes tape and reel. soic = 4k per reel. tssop = 5k per reel. 3. available in tape and reel and wafer form; order as sl788 for inkless wafer form. bumped die available upon request. please contact serial interface marketing. 9. at24hc02b ordering information ordering code voltage package operation range at24hc02b-pu (bulk form only) 1.8 8p3 lead-free/halogen-free/ industrial temperature ( ? 40 ? cto85 ? c) at24hc02bn-sh-b (1) (nipdau lead finish) 1.8 8s1 at24hc02bn-sh-t (2) (nipdau lead finish) 1.8 8s1 at24hc02b-th-b (1) (nipdau lead finish) 1.8 8a2 at24hc02b-th-t (2) (nipdau lead finish) 1.8 8a2 at24hc02b-w-11 (3) 1.8 die sale industrial temperature ( ? 40 ? cto85 ? c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8a2 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) options ? 1.8 low voltage (1.8v to 5.5v)
13 5134e?seepr?3/08 at24hc02b 10. part marking scheme 10.1 8-pdip 10.2 8-soic top mark seal year y = seal year ww = seal week | seal week 6: 2006 0: 2010 02 = week 2 | | | 7: 2007 1: 2011 04 = week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : a t m l h y w w 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = week 50 h 2 b 1 52 = week 52 |---|---|---|---|---|---|---|---| * lot number lot number to use all characters in marking |---|---|---|---|---|---|---|---| | bottom mark pin 1 indicator (dot) no bottom mark top mark seal year y = seal year ww = seal week | seal week 6: 2006 0: 2010 02 = week 2 | | | 7: 2007 1: 2011 04 = week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : a t m l h y w w 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = week 50 h 2 b 1 52 = week 52 |---|---|---|---|---|---|---|---| * lot number lot number to use all characters in marking |---|---|---|---|---|---|---|---| | bottom mark pin 1 indicator (dot) no bottom mark
14 5134e?seepr?3/08 at24hc02b 10.3 8-tssop top mark pin 1 indicator (dot) y = seal year ww = seal week | 6: 2006 0: 2010 02 = week 2 |---|---|---|---| 7: 2007 1: 2011 04 = week 4 * h y w w 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---| 9: 2009 3: 2013 :: : :::: :: h 2 b 1 50 = week 50 |---|---|---|---|---| 52 = week 52 bottom mark |---|---|---|---|---|---|---| p h |---|---|---|---|---|---|---| a a a a a a a |---|---|---|---|---|---|---| <- pin 1 indicator
15 5134e?seepr?3/08 at24hc02b 11. packaging information 11.1 8p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 8p3 , 8-lead, 0.300" wide body, plastic dual in-line package (pdip) 01/09/02 8p3 b notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba, for additional information . 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a ? ? 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 ? ? 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 to p v i e w side view end view
16 5134e?seepr?3/08 at24hc02b 11.2 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. note: 10/7/03 8s1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 b common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.00 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? 0 ? 8 ? top view end view side view e b d a a1 n e 1 c e1 l
17 5134e?seepr?3/08 at24hc02b 11.3 8a2 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 5/30/02 common dimensions (unit of measure = mm) symbol min nom max note d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 a ? ? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 8a2 , 8-lead, 4.4 mm body, plastic thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances , datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 8a2 b side view end view top view a2 a l l1 d 1 2 3 e1 n b pin 1 indicator this corner e e
18 5134e?seepr?3/08 at24hc02b 12. revision history doc. rev. date comments 5134e 9/2013 nrnd. replaced by at24hc02b 5134e 3/2008 added part marking scheme updated to new template 5134d 4/2007 removed reference to waffle pack on page 1 added lines to ordering code table shrink pin diagram; change to table 5; added two-wire software reset; removed lsb from figures 5134c 3/2007 pg. 12 - change to new catalog part number scheme. 5134b 9/2006 revision history implemented; added ?preliminary? status to datasheet.
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